RISC Processor
تفاصيل العمل
This project implements a five-stage, pipelined, Harvard processor with a RISC ISA in VHDL. The code structure is self-documenting, easy to follow, and prioritizes clarity, maintainability and extensibility. Each submodule in the Processor is self-contained. This makes modifications easier and within a limited scope.
مهارات العمل
